1. Field of the Invention
This invention relates to charge transfer devices used for image pick-up devices, and delay lines, comb filters, and transversal filters of the charge transfer type, and more particularly to the improvement of a portion of the charge transfer deviCe for applying a predetermined voltage to the drain region for draining unnecessary charges.
2. Description of the Related Art
There are various types of the signal output systems, which are employed in the output circuit of the charge transfer device (CTD) integrated on a semiconductor substrate. One of those signal output systems, which has been known, uses a floating diffusion region. In a known CTD employing this type of signal output system, a stepped-up voltage from a voltage step-up circuit is supplied to the drain region, in order to widen a dynamic range of the output signal. FIG. 1 shows a block diagram of an overall arrangement of a CTD with this voltage step-up circuit. FIG. 2 shows a sectional view of a part of the CTD when it is of the N channel buried type, for example. In FIGS. 1 and 2, reference numeral 41 designates an input terminal and 42 an output terminal. First power source terminal 43 is applied with the voltage of high potential power source VDD. Second power source terminal 44 is applied with the voltage of low potential power source VSS. Reference numeral 45 represents a P type semiconductor substrate. N.sup.- type buried channel region 46 is formed on this substrate 45. An insulating film is designated by numeral 47. Input section 48 receives an analog signal applied through input terminal 41, and biases the analog signal by a predetermined DC voltage to convert it into signal charges. Charge transfer section 49 transfers the signal charges from this input section. Floating diffusion region 50 as an N type diffusion region is provided adjacent to output gate electrode 51 at the final stage of this charge transfer section 49. Drain region 52 as an N type diffusion region is applied with a predetermined potential. A reset gate electrode 53 is formed on insulating film 47 layered on a portion of the substrate, which is located between floating diffusion region 50 and drain region 52. Reset pulse .phi.R, which varies between low and high voltages VRL and VRH, is applied to reset gate electrode 53. When reset pulse .phi.R is at high voltage VRH, the storage charges in floating diffusion region 50 are discharged into drain region 52, through the semiconductor region under this reset gate electrode 53.
MOS transistor 54 is of the enhancement type (referred to as E type), and for charge detection. This transistor is so arranged that its gate is connected to floating diffusion region 50, its drain is connected to high potential power source VDD, and its source is connected to output terminal 42. Current source circuit 55 is made up of at least one MOS transistor. Circuit 55 is connected at one end to charge detecting MOS transistor 54, and at the other end to low potential power source VSS. This circuit 55 and MOS transistor 54 make up an output circuit 56 of the source follower type. Output circuit 56 converts the signal charges stored in floating diffusion region 50 into a voltage signal.
Charge transfer section 49 is a 2-phase drive CTD, which is driven by, for example, transfer clocks .phi.1 and .phi.2 of two phases. The 2-phase drive CTD has pairs of transfer electrodes 57i and 58i (i=1 to n) made of polysilicon layers. These paired electrodes are for setting the charge transfer direction. One pair of these electrodes are provided for each phase of drive pulse. Output gate electrode 51 coupled with bias voltage VB is provided at the final stage of the drive CTD. Voltage step-up circuit 59 is for stepping up a predetermined voltage. The stepped-up voltage is applied as reset voltage VGG to drain region 52. Normally, this voltage VGG is set to be higher than the voltage of high potential power source VDD.
The operation of the CTD thus arranged will be described referring to a potential profile of FIG. 3. Input section 48 converts an analog signal with a proper bias DC voltage into a quantity of signal charge, which depends on its analog signal level. The signal charge is transferred, by charge transfer section 49, into floating diffusion region 50, and stored therein. The stored charge Q (shown in FIG. 3) is detected by output circuit 56 at predetermined timings, and converted into a voltage signal. The voltage signal is output at output terminal 42. At this time, reset pulse .phi.R is at low voltage VRL, and the potential PRL in the semiconductor region under reset gate electrode 53 electrically shuts off the path between the drain region 52 kept at reset voltage VGG level PD and floating diffusion region 50.
Then, when reset pulse .phi.R is at high voltage VRH, the potential PRH under reset gate electrode 53 allows a current to pass the path between floating diffusion region 50 and drain region 52. As a result, the charge stored in floating diffusion region 50 is discharged as unnecessary charge into drain region 52 after passing the semiconductor region under reset gate electrode 53. Further, the potential in floating diffusion region 50 is reset to the value PD in drain region 52, which amounts to reset voltage VGG.
A dynamic range DR of the output signal, which is to be detected by output circuit 56 and converted into a voltage signal, is expressed by a difference (PD-PG) of the potential PD of drain region 52 and the potential PG of the semiconductor region under output gate electrode 51. Since reset voltage VGG is higher than the voltage of high potential power source VDD, the dynamic range DR of the output signal can be considerably large by selecting the applying voltage VB of output gate electrode 51 to be low as possible in connection with the potential PnL in the semiconductor region under final stage transfer electrode 58n.
If the reset voltage VGG in drain region 52 is higher than power source VDD voltage, the high reset voltage is applied to the gate of the MOS transistor 54 in output circuit 56 when floating diffusion region 50 is reset. Assuming that the gate voltage of transistor 54 at the time of signal detection is VG (VG.apprxeq.VGG), a drain-source voltage is VDS, a gate-source voltage VGS, a threshold voltage is VTH, and a source voltage (at output terminal 42) is VO, we have EQU VDS=VDD-VO (1) EQU GS-VTH=VG-VO-VTH (2)
To obtain a saturation operation of MOS transistor 54 at the time of signal detection, the following relation must be held EQU VGS-VTH&lt;VDS (3)
Substituting the relation (1) into the relation (3), we have EQU VG-VTH&lt;VDD (4)
In case where a good linearity is required for the output signal, it is necessary to select the voltages so as to satisfy the relation (4) when the signal is detected.
FIG. 4 shows a circuit diagram of a specific arrangement of voltage step-up circuit 59 used in the CTD. Control pulses CP and CP used in this circuit are illustrated by a timing chart of FIG. 6. The arrangement of the voltage step-up circuit shown in FIG. 9 is a modification of the FIG. 4 circuit. In FIG. 4, reference numeral 61 designates a reference voltage source for producing reference voltage VREF; 62 a MOS transistor of the E (enhancement) type connected at the first terminal to this reference voltage source 61; 63 a MOS transistor of the E type connected at the first terminal to the second terminal of this MOS transistor 62; and 64 a capacitor connected at the first terminal to the connection point of both the MOS transistors. The second terminal of MOS transistor 63 is connected to the output terminal 65 for outputting the stepped-up voltage. Control pulse CP is applied to the second terminal of capacitor 64 and the gate of MOS transistor 63. Control pulse CP is applied to the gate of MOS transistor 62. At time t1 that control pulse CP is at "L" level or logical low, MOS transistor 62 is turned on, MOS transistor 63 is turned off, and capacitor 64 is charged by reference voltage VREF of reference voltage source 61 through MOS transistor 62. At time t2 that control pulse CP is at "H" level or logical high, MOS transistor 62 is turned off, MOS transistor 63 is turned on, the voltage at output terminal 65 is equal to the sum of reference voltage VREF and the peak value of control pulse CP.
It is a common practice that the power source VDD voltage or a reference voltage generating circuit using MOS transistors is used for the reference voltage source 61 used for voltage step-up circuit 59.
A specific example of the reference voltage generating circuit of this type is shown in FIG. 5, for example. The arrangements of the reference voltage generating circuits shown in FIGS. 7 and 8 are modifications of the FIG. 5 circuit. In the circuit of FIG. 5, two MOS transistors 66 and 67 of the depletion type (D type) are connected in series between the VDD voltage applying point and the VSS voltage applying point. The gates of these transistors are connected to the drains thereof. Reference voltage VREF is output from the series connection point of these transistors.
The conductivity type of D type MOS transistors 66 and 67 in the reference voltage generating circuit shown in FIG. 5 are the same as that of a D type MOS transistor made up of reset gate electrode 53, floating diffusion region 50, and drain region 52. Therefore, the threshold voltage VTH of each of these transistors is negative in polarity. The MOS transistor 54 of output circuit 56 is of the E type, and its threshold voltage is positive.
If the reference voltage generating circuit arranged as shown in FIG. 5 is used for the reference voltage source of the voltage step-up circuit of FIG. 4, some problems occur. The problems will be discussed below. To obtain a wide dynamic range DR of the CTD output signal, it is only needed that the potential PD formed in the semiconductor region under drain region 52 is increased by increasing the stepped-up voltage from voltage step-up circuit 59. If the bias voltage VFD in floating diffusion region 50 is set to excess the sum of the power source VDD voltage and the threshold voltage VTHE of transistor 54 (VDD+VTHE), transistor 54 operates in the nonsaturation region, so that the linearity of the output signal is damaged. Therefore, the upper limit of the stepped-up voltage in voltage step-up circuit 59 is equal to a maximum voltage allowing the linearity of the output signal to be kept, and can be mathematically expressed by EQU .vertline.VTHD.vertline.&lt;VFD&lt;VDD+VTHE (5)
where, EQU .vertline.VTHD.vertline.=PnL.apprxeq.PG
Voltage VTHD and VTHE vary as the process parameters in the device manufacturing stage, but their variations are a little for the reason that the reference voltage generating circuit of FIG. 5 uses the same conductivity type MOS transistors. Therefore, in the voltage step-up circuit of FIG. 4, the stepped-up voltage VGG is kept approximately constant against the variation of the process parameters. As a result, the operating range of bias voltage VFD is influenced by the process parameter variations, under the rule of the relation (5). Specifically, when the absolute value of threshold voltage VTHD is large, the lower limit margin of VFD is narrow, while when it is small, the upper limit margin of VFD is narrow. Therefore, when the absolute value VTHD is large, the dynamic range DR is narrow. When it is small, the MOS transistor 54 of output circuit 56 is saturated. Stepped-up voltage VGG must be set to be low. Also in this case, the dynamic range DR is small.
As described above, in the output circuit of the conventional CTD, the margin of the maximum amplitude range of the signal in the floating diffusion region necessary for keeping the linearity of the output signal is narrow under influence of the process parameters, particularly the threshold voltage of the depletion type MOS transistor.